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supersedes october 1996 version, ds3707 - 4.2 ds3707 - 5.3 october 1997 pdsp16116 16 x 16 bit complex multiplier features complex number (16 1 16) 3 (16 1 16) multiplication full 32-bit result 20mhz clock rate block floating point fft butterfly support ( 2 1) 3 ( 2 1) trap twos complement fractional arithmetic ttl compatible i/o complex conjugation 2 cycle fall through 144-pin pga or qfp packages applications fast fourier transforms digital filtering radar and sonar processing instrumentation image processing ordering information pdsp16116 mc ggdr 10mhz mil-883 screened pdsp16116a b0 ac 20mhz industrial pdsp16116a a0 ac 20mhz military pdsp16116a b0 gg 20mhz industrial pdsp16116a mc ggdr 20mhz mil-883 screened pdsp16116b b0 ac 25mhz industrial pdsp16116d b0 gg 31?mhz industrial associated products pdsp16318/a complex accumulator pdsp16112/a (16 1 16) 3 (12 1 12) complex multiplier pdsp16330/a pythagoras processor pdsp1601/a alu and barrel shifter pdsp16350 precision digital modulator pdsp16256 programmable fir filter pdsp16510 single chip fft processor fig. 1 simplified block diagram pr15:0 add/sub reg mult reg reg mult reg reg mult reg reg mult reg add/sub shift reg shift reg pi15:0 xr15:0 xi15:0 yr15:0 yi15:0 the pdsp16116 contains four 16 3 16 array multipliers, two 32-bit adder/subtractors and all the control logic required to sup- port block floating point arithmetic as used in fft applications. the pdsp16116a variant will multiply two complex (16 1 16) bit words every 50ns and can be configured to output the com- plete complex (32 1 32) bit result within a single cycle. the data format is fractional twos complement. in combination with a pdsp16318a, the pdsp16116a forms a two-chip 20mhz complex multiplier accumulator with 20-bit accumulator registers and output shifters. the pdsp16116a in combination with two pdsp16318as and two pdsp1601as forms a complete 20mhz radix 2 dit fft butterfly solution which fully supports block floating point arithmetic. the pdsp16116 has an extremely high throughput that is suited to recursive algorithms as all calculations are performed with a single pipeline delay (two cycle fall-through).
pdsp16116 2 system features the pdsp16116 has a number of features tailored for sys- tem applications. ( 2 1) 3 ( 2 1) trap in multiply operations using twos complement fractional no- tation, the ( 2 1) 3 ( 2 1) operation forms an invalid result because 1 1 is not representable in the fractional number range. the pdsp16116 eliminates this problem by trapping the ( 2 1) 3 ( 2 1) operation and forcing the multiplier result to become the most positive representable number. complex conjugation many algorithms using complex arithmetic require conjuga- tion of complex data stream. this operation has traditionally re- quired an additional alu to multiply the imaginary component by -1. the pdsp16116 eliminates this requirement by offering on-chip complex conjugation of either of the two incoming com- plex data words with no loss in throughput. easy interfacing as with all pdsp family members the pdsp16116 has reg- istered l/o for data and control. data inputs have independent clock enables and data outputs have independent three state output enables. signal xr15:0 xl15:0 yr15:0 yl15:0 pr15:0 pl15:0 clk conx cony round mbfp ar15:1 3 al15:1 3 wta1:0 wtb1:0 wtout1:0 sfta1:0 sftr2:0 gwr4:0 osel1:0 v dd gnd type input input input input output output input input input input input input input input input input input input input output output output output input input power power description 16-bit input for real x data 16-bit input for imaginary x data 16-bit input for real y data 16-bit input for imaginary y data 16-bit output for real p data 16-bit output for imaginary p data clock; new data is loaded on rising edge of clk clock, enable x-port input register clock, enable y-port input register conjugate x data conjugate y data rounds the real and imaginary results mode select (bfp/normal) start of bfp operations (see note 1) end of pass (see note 1) 3 msbs from real part of a-word (see note 1) 3 msbs from imaginary part of a-word (see note 1) word tag from a-word word tag from b-word/shift control (see note 2) word tag output (see note 1) shift control for a-word / overflow flag (see note 2) shift control for accumulator result (see note 1) global weighting register contents (see note 1) selects the desired output configuration output enables 1 5v supply (see note 3) 0v supply (see note 3) normal mode configuration tie low tie low tie low tie low tie low tie low notes 1. used only in bfp mode 2. performs different functions in bfp/normal modes 3. all supply pins must be connected table 1 signal descriptions cex cey sobfp eopss oer, oei
pdsp16116 3 fig. 2 pdsp16116 block diagram add/sub decode reg reg 16 3 16 mult mux xr15:0 c o m p reg reg mux xi15:0 c o m p reg reg mux yr15:0 c o m p reg reg mux yi15:0 c o m p 16 3 16 mult 16 3 16 mult 16 3 16 mult add/sub conx cony shift reg shift reg mux mux ovr cey cex control logic clk wta ar15:13 wtb ai15:13 sobpf eopss sftr sfta gwr4:0 wtout round osel round osel oer oei pr15:0 pi15:0 internal signals ?
pdsp16116 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a b c d e f g h j k l m n p r pin 1 ident (see note 2) pin 144 pin 1 fig. 3a pin connections for 144 i/o power pin grid array package (bottom view) fig. 3b pin connections for 144 i/o ceramic quad flatpack (top view) fig. 3 pin connection diagrams (not to scale). see table 1 for signal descriptions and table 2 for pinouts. ac144 (power) gg144
pdsp16116 5 signal v dd gnd pr13 pr12 pr11 pr10 pr9 pr8 pr7 pr6 pr5 gnd v dd pr4 pr3 pr2 pr1 pr0 pi0 pi1 pi2 pi3 pi4 v dd pi5 gnd pi6 pi7 pi8 pi9 pi10 pi11 pi12 pi13 gnd v dd gg 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 signal pi14 pi15 wtout1 wtout0 sftr0 sftr1 sftr2 oei cony conx round ai13 ai14 ai15 ar13 ar14 ar15 yi15 yi14 yi13 yi12 yi11 yi10 yi9 yi8 yi7 yi6 yi5 yi4 yi3 yi2 yi1 yi0 xi0 gnd v dd ac d3 c2 b1 d2 e3 c1 e2 d1 f2 f3 e1 g2 g3 f1 g1 h2 h1 h3 j3 j1 k1 j2 k2 k3 l1 l2 m1 n1 m2 l3 n2 p1 m3 n3 b2 a1 gg 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 signal xi1 xi2 xi3 xi4 xi5 xi6 xi7 xi8 xi9 xi10 xi11 xi12 xi13 xi14 xi15 cey cex xr15 xr14 xr13 xr12 xr11 xr10 xr9 xr8 xr7 xr6 xr5 xr4 xr3 xr2 xr1 xr0 yr15 yr14 yr13 ac n4 p3 r2 p4 n5 r3 p5 r4 n6 p6 r5 p7 n7 r6 r7 p8 r8 n8 n9 r9 r10 p9 p10 n10 r11 p11 r12 r13 p12 n11 p13 r14 n12 n13 p14 r15 gg 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 signal gnd v dd yr12 yr11 yr10 yr9 yr8 yr7 yr6 yr5 yr4 yr3 yr2 yr1 yr0 eopss v dd sobfp wtb1 wtb0 wta1 wta0 mbfp clk osel1 osel0 oer sfta0 sfta1 gwr0 gwr1 gwr2 gwr3 gwr4 pr15 pr14 ac p2 r1 p15 m14 l13 n15 l14 m15 k13 k14 l15 j14 j13 k15 j15 h14 h15 h13 g13 g15 f15 g14 f14 f13 e15 e14 d15 c15 d14 e13 c14 b15 d13 c13 b14 a15 gg 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 ac n14 m13 a14 b12 c11 a13 b11 a12 c10 b10 a11 b13 c12 a10 a9 b8 a8 c8 c7 a7 a6 b7 b6 c6 a5 b5 a4 a3 b4 c5 b3 a2 c4 c3 b9 c9 note. all gnd and v dd pins must be used table 2 pin connections for ac144 (power) and gg144 packages
pdsp16116 6 normal mode operation when the mbfp mode select input is held low the ?ormal mode of operation is selected. this mode supports all complex multiply operations that do not require block floating point arithmetic. complex twos complement fractional data is loaded into the x and y input registers via the x and y ports on the rising edge of clk. the x and y port registers are individually enabled by the cex and cey signals respectively. if the registers are re- quired to be permanently enabled, then these signals may be tied to ground. the real and imaginary components of the fractional data are each assumed to have the following format: bit number 15 weighting 14131211109 76543210 s 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 6 2 5 2 4 2 3 2 2 2 1 8 2 7 where s = sign bit, which has an effective weighting of 2 2 0 the value of the 16-bit twos complement word is ( 2 1 3 s) 1 (bit14 3 2 2 1 ) 1 (bit13 3 2 2 2 ) 1 (bit12 3 2 2 3 ) multiplier stage on each clock cycle the contents of the input registers are passed to the four multipliers to start a new complex multiply operation. each complex multiply operation requires four partial products (xr 3 yr), (xr 3 yi), (xi 3 yr), (xi 3 yi), all of which are calculated in parallel by the four 16 3 16 multipliers. only one clock cycle is required to complete the multiply stage before the multiplier results are loaded into the multiplier output registers for passing on to the adder/ subtractors in the next cycle. each multiplier produces a 31- bit result with the duplicate sign bit eliminated. the format of the output data from the multipliers is: bit number 30 weighting 292827262524 76543210 s 2 30 2 29 2 28 2 27 2 26 2 25 2 24 2 23 2 6 2 5 2 4 2 3 2 2 2 1 the effective weighting of the sign bit is 2 2 0 adder/subtractor stage the 31-bit real and imaginary results from the multipliers are passed to two 32-bit adder/subtractors. the adder calcu- lates the imaginary result [(xr 3 yi) 1 (xi 3 yr)] and the rounding the round control when asserted rounds the most significant 16 bits of the full 32-bit result from the shifter. if the round signal is active (high), then bit 16 is set to ?? rounding the most significant 16 bits of the shifted result. (the least significant 16 bits are unaffected). inserting a ? ensures that the rounding error is never greater than 1 lsb and that no dc bias is introduced as a result of the rounding processes. the format of the rounded result is: the effective weighting of the sign bit is 2 2 1 bit number 30 weighting 29 28 27 17 16 15 14 13 2 1 0 s 2 30 2 29 2 28 2 17 2 16 2 15 2 14 2 13 2 3 2 2 2 1 2 0 31 18 2 1 2 rounded value lsbs the effective weighting of the sign bit is 2 2 1 bit number 30 weighting 29282726 76543210 s 2 30 2 29 2 28 2 27 2 26 2 25 2 24 2 23 2 4 2 3 2 2 2 1 2 0 31 8 2 22 subtractor calculates the real result (xr 3 yr) = (xi 3 yi). each adder/subtractor produces a 32-bit result with the following format: result correction due to the nature of the fraction twos complement repre- sentation it is possible to represent 2 1 exactly but not 1 1. with conventional multipliers this causes a problem when 2 1 is mul- tiplied by 2 1 as the multiplier produces an incorrect result. the pdsp16116 includes a trap to ensure that the most positive number (value = 1? 2 30 , hex = 7ffffffff) is substituted for the incorrect result. the multiplier result is therefore always a correct fractional value. fig.2 shows the value ??being multi- plexed into the data path controlled by four comparators. complex conjugation either the x or y input data may be complex conjugated by asserting the conx or cony signals respectively. asserting either of these signals has the effect of inverting (multiplying by 2 1 ) the imaginary component of the respective input. table 3 shows the effect of conx and cony on the x and y inputs. table 3 conjugate functions cony conx low high low high low low high high function (xr 1 xi) 3 (yr 1 yi) (xr 2 xi) 3 (yr 1 yi) (xr 1 xi) 3 (yr 2 yi) invalid operation x 3 y conj. x 3 y x 3 conj. y invalid
pdsp16116 7 shifter each of the two adder/subtractors are followed by shifters controlled via the wtb control input. these shifters can each apply two different shifts; however, the same shift is applied to both real and imaginary components. the four shift options are: 1. wtb1:0 = 11 shift complex product one place to the left, giving a shifter output format: bit number 30 weighting 29282726 76543210 s 2 30 2 29 2 28 2 27 2 26 2 25 2 24 2 4 2 3 2 2 2 1 31 25 2 5 2 6 2 31 the effective weighting of the sign bit is 2 2 0 bit number 30 weighting 29282726 76543210 s 2 30 2 29 2 28 2 27 2 26 2 25 2 24 2 4 2 3 2 2 2 0 31 2 1 8 2 22 2 23 2. wtb1:0 = 00 no shift applied, giving a shifter output format: bit number 30 weighting 29282726 6543210 s 2 29 2 28 2 27 2 26 2 25 2 24 2 4 2 3 2 2 2 0 31 2 1 2 23 2 1 25 2 5 24 the effective weighting of the sign bit is 2 2 2 the effective weighting of the sign bit is 2 2 1 the effective weighting of the sign bit is 2 2 3 4. wtb1:0 = 10 shift complex product two places to the right, giving a shifter output format: bit number 30 weighting 29282726 6543210 s 2 28 2 27 2 26 2 25 2 24 2 4 2 3 2 2 2 0 31 2 1 2 23 2 1 25 24 2 2 2 22 3. wtb1:0 = 01 shift complex product one place to the right, giving a shifter output format: pin descriptions xr, xi, yr, yi data inputs, 16 bits. data is loaded into the input registers from these ports on the rising edge of clk. the data format is fractional twos complement, where the msb (sign bit) is bit 15. in normal mode the weighting of the msb is 2 2 0 i.e. 2 1. pr, pi data outputs, 16 bits. data is clocked into the output regis- ters and passed to the pr and pi outputs on the rising edge of clk. the data format is fractional twos complement. the field of the internal result selected for output via pr and pi is control- led by signals osel1:0 (see table 4). clk common clock to all internal registers clock enables for x and y input ports. when low these inputs enable the clk signal to the x or y input registers, allowing new data to be clocked into the multiplier. conx, cony conjugate controls. if either of these inputs is high on the rising edge of clk, then the data on the associated input has its imaginary component inverted (multiplied by 2 1), see table 3. conx and cony affect data input on the same clock rising edge. round the round control pin is used to round the most significant 16 bits of the output register. the round input is not latched and is intended to be tied high or low depending upon the application. msr and lsr are the most and least siginificant 16-bit words of the real shifter output, msl and lsl are the most and least significant 16-bit words of the imaginary shifter output. the output select options allow two different modes for ex- tracting the full 32-bit result from the pdsp16116. the first mode treats the two 16-bit outputs as real and imaginary ports, allow- ing the real and imaginary results to be output in two halves on the real and imaginary output ports. the second mode treats the two 16-bit outputs as one 32-bit output and allows the real and imaginary results to be output as 32-bit words. table 4 output selection overflow if the left shift option is selected and the adder/subtractor contains a 32-bit word, then an invalid result will be passed to the output. an invalid output arising from this combination of events will be flagged by the sfta0 flag output. the sfta0 flag will go high if either the real or imaginary result is invalid. output select the output from the shifters is passed to the output select mux, which is controlled via the osel inputs. these inputs are not registered and hence allow the output combination to be changed within each cycle. the full complex 64-bit result from the multiplier may therefore be output within a single cycle. the osel control selects four different output combinations as summarised in table 4. osel1 0 1 0 1 p1 pr osel0 msr lsr msr msi 0 0 1 1 msi lsi lsr lsi cex, cey
pdsp16116 8 mbfp mode select. when high, block floating point (bfp) mode is selected. this allows the device to maintain the dynamic range of the data using a series of word tags. this is especially useful in fft applications. when low, the chip operates in normal mode for more general applications. this pin is intended to be tied high or low, depending on application. wtout1:0 (bfp mode only) word tag output. this tag records the weighting of the output words from the current cycle relative to the current global weighting register (see table 6). it should be stored along with the a and b words as it will form the input word tags, wta and wtb, for each complex word during the next pass. in normal mode, wtout1:0 are not used and should be left unconnected. weighting of the output relative to the current global weighting register wtout1:0 one less the same one more two more 00 01 10 11 table 6 word tag weightings function wtb1:0 shift complex product 1 place to the left no shift applied shift complex product 1 place to the right shift complex product 2 places to the right 11 00 01 10 table 7 normal mode shift control sfta1:0 (bfp and normal modes) in bfp mode, these signals act as the a-word shift control. they allow shifting from one to four places to the right, (see table 8). depending on the relative weightings of the a-words and the complex product, the a-word may have to be shifted to the right to ensure compatible weightings at the inputs to the pdsp16318 complex accumulator. the two words must have the same weighting if they are to be added. in normal mode, sfta0 performs a different function. if wtb1:0 is set to implement a left shift, then overflow will occur if the data is fully 32 bits wide. this pin is used to flag such an overflow. sfta1 is not used in normal mode. function sfta1:0 shift a-word 1 place to the right shift a-word 2 places to the right shift a-word 3 places to the right shift a-word 4 places to the right 00 01 10 11 wta1:0 (bfp mode only) word tag from the a-word. this word records the weighting of the a-word relative to the global weighting register on the previous pass. although the a-word itself is not processed in the pdspl 6116, this information is required by the control logic for the radix 2 butterfly fft application. these inputs should be tied low in normal mode. wtb1:0 (bfp and normal modes) in bfp mode, this is the word tag from the b-word. this is operated in the same manner as wta but for the b-word. the value of the word tags are used to ensure that the binary weight- ing of the a-word and the product of the complex multiplier are the same at the inputs to the complex accumulator. depending on which word is the larger, the weighting adjustment is per- formed using either the internal shifter or an external shifter con- trolled by sfta. the word tags are also used to maintain the weighting of the final result to within plus two and minus one binary points relative to the new gwr. (on the first pass all word tags will be ignored). in normal mode. these inputs per- form a different function. they directly control the internal shifter at the output port as shown in table 7. table 8 external a-word shift control gwr4:0 (bfp mode only) contents of the global weighting register. the gwr stores the weighting of the largest word present with respect to the weighting of the original input words. hence, if the contents of the gwr are 00010, it indicates that the largest word currently being processed has its binary point two bits to the right of the original data at the start of the bfp calculations. the contents of this register are updated at the end of each pass, according to the largest value of wtout occuring during that pass. for example, if wtout = 11, then gwr will be increased by 2 (see table 6). the gwr is presented in twos complement format. in normal mode, gwr4:0 are not used and should be left unconnected. start of bfp. this input should be held low for the first cycle of the first pass of the bfp calculations (see fig.7). it serves to reset the internal registers associated with bfp control. when operating in normal mode this input should be tied low. end of pass. this input should be held low for the last cycle of each pass and for the lay time between passes. it instructs the control logic to update the value of the global weighting reg- ister and prepare the bfp circuitry for the next pass. when op- erating in normal mode this input should be tied low. ar15:13 (bfp mode only) three msbs of the real part of the a-word. these are used in the fft butterfly application (see fig. 4) to determine the magnitude of the real part of the a-word and, hence, to deter- mine if there will be any change of word growth in the pdsp16318 complex accumulator. when operating in normal mode, these inputs are not used and may be tied low. ai15:13 (bfp mode only) three msbs of the imaginary part of the a-word. used in the same fashion as ar15:13. sftr2:0 (bfp mode only) accumulator result shift control. these pins should be linked directly to the s2:0 pins on the pdsp16318 complex accumulator. they control the accumulators barrel shifter (see table 5). the purpose of this shift is to minimise sign extension in the multiplier or accumulator alus. in normal mode, sftr2:0 are not used and should be left unconnected. table 5 accumulator shifts (bfp mode) sftr2:0 000 001 010 011 100 101 110 111 reserved reserved reserved shift right by one no shift shift left by one shift left by two reserved function sobfp (bfp mode only) eopss (bfp mode only)
pdsp16116 9 osel1 :0 the outputs from the device are selected by the osel0 and osel1 instruction bits. these controls allow selection of the output combination during the current cycle (they are not registered). there are four possible output configurations that allow either complex outputs of the most or least signifi- cant bytes, or real or imaginary outputs of the full 32-bit word (see table 4). osel0 and osel1 should both be tied low when in bfp mode. bfp mode fft application the pdsp16116 may be used as the main arithmetic unit of the butterfly processor, which will allow the following fft bench- marks: 1024-point complex radix 2 transform in 517 s 512-point complex radix 2 transform in 235 s 256-point complex radix 2 transform in 106 s in addition, with pin mbfp tied high, the bfp circuitry within the pdsp16116 can be used to adaptively rescale data through- out the course of the fft so as to give high-resolution results. the bfp system on the pdsp16116 can be used with any vari- ation of the radix 2 decimation-in-time (dit) fft, for example, the constant geometry algorithm, the in-place algorithm etc. an n-point radix 2 dit fft is split into log(n) passes. each pass consists of n/2 ?utterflies? each performing the operation: a = a 1 bw b = a 2 bw where w is the complex coefficient and a and b are the complex data. fig.4 illustrates how a single pdsp16116 may be combined with two pdsp1601s and two pdsp16318s to form a complete bfp butterfly processor. the pdsp16318s are used to perform the complex addition and subtraction of the butterfly operation, while the pdsp1601s are used to match the data path of the a-word to the pipelining and shifting opera- tions within the pdsp16116. for more information on the theory and construction of this butterfly processor, refer to application note an59. bfp mode operation the bfp mode on the pdsp16116 is intended for use in the fft application described above, that is, it is intended to pre- vent data degradation during the course of an fft calculation. the operation of the pdsp16116-based bfp buttertly proces- sor (see fig.4) is described below. the block floating point system a block floating point system is essentially an ordinary inte- ger arithmetic system with some additional logic, the purpose of which is to lend the system some of the enormous dynamic range afforded by a true floating point system without suffering the corresponding loss in perlormance. the initial data used by the fft should all have the same binary arithmetic weighting. in other words, the binary point should occupy the same position in every data word as is nor- mal in integer arithmetic. however, during the course of the fft, a variety of weightings are used in the data words to increase the dynamic range available. this situation is similar to that within a true floating point system, though the range of numbers rep- resentable is more limited. in the bfp system used in the pdsp16116, there are, within any one pass of the fft, four possible positions of the binary point wihin the integer words. to record the position of its binary point, each word has a 2-bit word tag associated with it. by way of example, in a particular pass the following four positions of binary point may be avail- able, each denoted by a certain value of word: xx?xxxxxxxxxxx word tag = 00 xxx?xxxxxxxxxx word tag = 01 xxxx?xxxxxxxxx word tag = 10 xxxxx?xxxxxxxx word tag = 11 at the end of each constituent pass of the fft, the positions of the binary point supported may change to reflect the trend of data increase or decreases in magnitude. hence, in the pass following that of the above example, the four positions of binary point supported may be changed to: xx?xxxxxxxxxxx word tag = 00 xxx?xxxxxxxxxx word tag = 01 xxxx?xxxxxxxxx word tag = 10 xxxxx?xxxxxxxx word tag = 11 this variation in the range of binary points supported from pass to pass (i.e. the movement of the binary point relative to its position in the original data) is recorded in the gwr. thus, the position of the binary point can be determined relative to its ini- tial position by modifying the value of gwr by wtout for a given word as shown in table 6. as an example, if gwr=01001 and wtout=10 then the binary point has moved 10 places to the right of its original position. pdsp16116/a xr xi yr yi br bi wr wi wta wtb eopss sobfp pr pi pdsp1601/a a c ai ai15:13 pdsp1601/a a c ar ar15:13 pdsp16318/a ab cd pdsp16318/a ba cd wtout gwr a ra ib rb i dar dai sfta sfta sftr sftr oer oei fig. 4 fft butterfly processor
pdsp16116 10 the butterfly operation the butterfly operation is the arithmetic operation which is repeated many times to produce an fft. the pdsp16116- based butterfly processor performs this operation in a low power high accuracy chip set. a new butterfly operation is commenced each cycle, requir- ing a new set ot data for b, w, wta and wtb. five cycles later, the corresponding results a and b are produced along with their associated wtout. in between, the signals sfta and sftr are produced and acted upon by the shifters in the pdsp1601/a and pdsp16318/a. the timing of the data and control signals is shown in fig.6. the results (a and b ) of each butterfly calculation in a pass must be stored to be used later as the input data (a and b) in the next pass. each result must be stored together with its as- sociated word tag, wtout. although wtout is common to both a and b , it must be stored separately with each word as the words are used on different cycles during the next pass. at the inputs, the word tag associated with the a word is known as wta and the word tag associated with the b word is known as wtb. hence, the wtouts from one pass will become the wtas and wtbs for the following pass. it should be noted that the first pass is unique in that word tags need not be input into the but- terfly as all data initially has the same weighting. hence, during the first pass alone, the inputs wta and wtb are ignored. fig. 5 butterfly operation control of the fft to enable the block floating point hardware to keep track of the data, the following signals are provided: sobfp - start of the fft eopss - end of current pass these inform the pdspl 6116/a when an fft is starting and when each pass is complete. fig.7 shows how these signals should be used and a commentary is provided below. to begin the fft, the signal eopss should be set high (where it will remain for the duration of the pass). sobfp should be pulled low during the initial cycle when the first data words a and b are presented to the inputs of the butterfly processor. the following cycle sobfp must be pulled high where it should remain for the duration of the fft. new data is presented to the processor each successive cycle until the end of the first pass of the fft. on the last cycle of the pass, the eopss should be pulled low and held low for a minimum of five cycles, the time required to clear the pipeline of the butterfly processor so that all the results from one pass are obtained before beginning the following pass. should a longer pause be required between passes ?to ar- range the data for the next pass, for example ?then eopss may clk n 1 1 n 1 2 n 1 3 n 1 4 n 1 4 n 1 1 n 1 2 n 1 3 n 1 4 n 1 4 n 1 1 n 1 2 n 1 3 n 1 4 n 1 4 n 2 1 n 1 1 n 1 2 n 1 3 n 2 2 n 1 1 n 1 2 n 1 1 n 1 2 n 1 1 n 1 2 n 2 4 n 2 3 n 2 2 n 2 1 n 1 1 n 2 1 n n n n n n n n n n 2 2 n 2 3 n 2 3 n 2 3 n 2 5 n 2 5 n 2 2 n 2 2 n 2 1 n 2 1 n 2 1 n 2 3n 2 2 br, bi, wr, wi wta, wtb ar, ai sfta sftr pr, pi dar, dai wtout a r, a i, b r, b i fig. 6 butterfly data and control signals fft output normalisation when an fft system outputs a series of fft results for display, storage or transmission, it is essential that all results are compatible, i.e. with the binary point in the same position. however, in order to preserve the dynamic range of the data in the fft calculation, the pdsp1601/a employs a range of dif- ferent weightings. therefore, data must be re-formatted at the end of the fft to the pre-determined common weighting. this can be done by comparing the exponent of given data word with the pre-determined universal exponent and then shifting the data word by the difference. the pdsp1601/a, with its multifunction 16-bit barrel shifter, is ideally suited to this task. according to theory, the largest possible data result from an fft is n times the largest input data. this means that the bi- nary point can move a maximum of log 2 (n) places to the right. hence, if the universal exponent is chosen to be log 2 (n) this should give a sufficient range to represent all data points faithfully. aa bb a = a 1 bw b = a 2 bw w be kept low as long as necessary; the next pass cannot com- mence until it is brought high again. on the initial cycle of each new pass, the signal eopss should be pulled high and it should remain high until the final cycle of that pass, when it is pulled low again.
pdsp16116 11 clk n 2 4n 2 3n 2 2n 2 1 n 2 5 a , b , btout sobfp eopss a, b, w, wta, wtb gwr 234567 n 2 123 23 1 1 n 1 1 n start of first pass end of first pass/ start of next pass (minimum number of lay cycles shown). period between other intermediate passes is similar. notes 1. 1 = first cycle of data in pass 2. n = last cycle of data in pass in practice, data output may never approach the theoretical maximum. hence, it may be worthwhile to try various universal exponents and choose the one best suited to the particular ap- plication. data is output from the butterfly processor with a two-part exponent: the 5-bit gwr applicable to all data words from a given fft and a 2-bit wtout associated with each individual dataword. to find the complete exponent for a given word, the gwr for that fft must be modified by its wtout as shown in table 6. the result is the number of places the binary point has shifted to the right during the course of the fft. this value must be compared with the universal exponent to determine the shift required. this is done by subtracting it from the universal exponent. the number of places to be shifted is equal to the difference between the two exponents. the shift can be implemented in a pdsp1601/a (the shift value is fed into the sv port). as fft data consists of real and imaginary parts, either two pdsp1601/as must be used (controlled by the same logic) or a single pdsp1601/a could be used handling real and imaginary data on alternate cycles (using the same instructions for both cycles). an example of an output normalisation circuit is shown in fig.8. only 4-bit data paths are used in calculating the shift. this means that we must be able to trap very small values negative of gwr and force a 15-bit right shift in such cases. nb it is easier to simply add the word tag to the exponent for the purpose of determing the shift required, instead of modifying it according to table.6. to compensate for this, the universal ex- ponent may be increased by one. fig. 8 output normalisation circuit 4-bit adder gwr wtout 4-bit subtractor universal exponent 4-bit mux 1111 sign bit 16-bit data pdsp1601 sv port b port c port asrsv normalised output data fig. 7 use of the bfp control signals
pdsp16116 12 clk input data x and y output p ports output sfta1:0 valid data input controls cex and cey t cp t ds t dh t clk t clkh t clkl t csfta t csfta valid data t cons t ces t ceh t conh t ws t wh input controls conx and cony input control wtb1:0 fig. 9 normal mode timing oer and oei output p ports high z t oplz t opzl high z t opzh t ophz high z fig. 10 output tristate timing v h 0?v delay from output high to output high z (t ophz ) 0?v 0?v 0?v v l 1?v 1?v delay from output low to output high z (t oplz ) delay from output high z to output low (t opzl ) delay from output high z to output high (t opzh ) test waveform measurement level v h is the voltage reached when the output is driven high v l is the voltage reached when the output is driven low v t = 0v v t = v dd three state delay measurement load v t dut 30p 1?k fig. 11 three state delay measurement
pdsp16116 13 electrical characteristics the electrical characteristics are guaranteed over the following range of operating conditions, unless otherwise stated: v dd = 1 5v 10%, gnd = 0v, t amb (industrial) = 2 40 c to 1 85 c, t amb (military) = 2 55 c to 1 125 c static characteristics min. typ. max. output high voltage output low voltage input high voltage input high voltage input low voltage input leakage current input capacitance output leakage current output short circuit current 10 - 0? - - 0? 1 10 1 50 300 2? - 3? 2? - 2 10 2 50 10 v oh v ol v ih v ih v il i in c in i oz i os i oh = 8ma i ol = 2 8ma clk input only all other inputs gnd < v in < v dd gnd < v out < v dd v dd = 1 5?v v v v v v a pf a ma units value conditions characteristic symbol p ports setup time wtout1:0 setup time gwr4:0 setup time sfta1:0 setup time sftr2:0 setup time cex or cey setup time cex or cey hold time x or y ports setup time x or y ports hold time wta, wtb, sobfp or eopss setup time wta, wtb, sobfp or eopss hold time conx or cony setup time conx or cony hold time ar15:13 or ai15:13 setup time ar15:13 or ai15:13 hold time osel to valid p ports oer or oei high to pr or pi high to high z oer or oei low to pr or pi low to high z oer or oei low to pr or pi high z to high oer or oei high to pr or pi high z to low clk frequency clk period clk high time clk low time v dd current (cmos input levels) v dd current (ttl input levels) characteristic switching characteristics symbol t cp t cw t cg t csfta t csftr t ces t ceh t ds t dh t ws t wh t cons t conh t as t ah t op t ophz t oplz t opzh t opzl f clk t clk t clkh t clkl i ddc i ddt max. min. max. min. 45 30 30 60 50 - 0 - 2 - 0 - 0 - 0 35 35 45 22 24 10 - - - 60 100 5 5 5 5 5 11 - 11 - 14 - 14 - 14 - - - - - - 100 30 20 - - pdsp16116a 5 5 5 5 5 8 - 8 - 8 - 8 - 8 - - - - - - 50 12 12 - - 23 20 20 30 28 - 0 - 0 - 0 - 0 - 0 20 25 25 18 18 20 - - - 80 130 pdsp16116 conditions notes 1. v dd = 1 5?v, outputs unloaded, clock frequency = max. 2. the pdsp16116b is specified as the pdsp16116a except that the maximum clock frequency is guaranteed at 25mhz, with a minimum clock period of 40ns. fig. 9 9 9 9 9 9 9 9 9 9 10, 11 10, 11 10, 11 10, 11 9 9 9 max. min. pdsp16116d 5 5 5 5 5 8 - 8 - 8 - 8 - 8 - - - - - - 31? 12 12 - - 23 20 20 30 28 - 0 - 2 - 0 - 0 - 2 20 25 25 18 18 31? - - - 80 130 units 30pf 30pf 30pf 30pf 30pf 30pf see note 1 see note 1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns mhz ns ns ns ma
pdsp16116 14 absolute maximum ratings (note 1) supply voltage, v dd input voltage, v in output voltage, v out clamp diode current per pin, i k (see note 2) static discharge voltage (hbm) storage temperature, t s ambient temperature with power applied, t amb military grade industrial grade junction temperature package power dissipation thermal resistances junction-to-case, jc junction-to-ambient, ja 2 0?v to 1 7?v 2 0?v to v dd 1 0?v 2 0?v to v dd 1 0?v 18ma 500v 2 65 c to 1 150 c 2 55 c to 1 125 c 2 40 c to 1 85 c 120 c 1000mw 12 c/w 29 c/w notes 1. exceeding these ratings may cause permanent damage. functional operation under these conditions is not implied. 2. maximum dissipation should not be exceeded for more than1 second, only one output to be tested at any one time. 3. exposure to absolute maximum ratings for extended periods may affect device reliablity.

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